1. Field of the Invention
The present invention relates generally to semiconductor manufacturing and, more particularly, to halftone photomasks.
2. Description of Related Art
One of the processing steps used during a semiconductor manufacturing process is photolithography. Photolithography is implemented numerous times during the manufacturing process and is one of the more important as well as one of the more limiting processes for determining a maximum density and final reliability of the integrated circuits. Photolithography can be particularly important in positioning the transistors, interconnect layers and via and in ensuring their uniformity.
A typical photolithographic process is implemented by depositing onto a working surface, by means such as a spinner, a layer of photosensitive resist that can be patterned by exposure to ultraviolet (UV) light or another radiation type. The working surface may be a semiconductor wafer, interconnect layer or other layer depending on the current manufacturing stage of the integrated circuits. The photoresist layer is sensitive to light and may be patterned based on exposing the photoresist to a corresponding pattern of light.
To undergo exposure, the photoresist-covered wafer is placed beneath a photomask designed to prevent the penetration of radiation through certain portions of the photoresist. Predetermined areas of the photoresist then undergo a degree of polymerization or depolymerization, which can be a function of the nature and extent of photoresist exposure.
The photomask forms the pattern by utilizing areas that block the light and other areas that allow the light to pass from the light source to the photoresist layer. The pattern of light created by the photomask is typically for a single die on a wafer. A lens may be positioned between the photomask and the photoresist layer to reduce the size of the pattern and to focus the pattern of light onto the die. The lithography tool steps from one die to the next die on the wafer and repeats the process until all selected die on the wafer have been exposed to the pattern of light created by the photomask.
A chemical bath known as a developer can then be used to dissolve parts of the photoresist that remain relatively depolymerized after the exposure by placing the wafer therein and allowing the wafer to be rinsed for a designated time period. Having received the pattern from the photomask, the layer of photoresist on the wafer is typically referred to as a layer of patterned photoresist. The presence or absence of photoresist across a working surface creates a pattern or template to be used by subsequent processing steps of the integrated circuit. For example, an etching or an ion implantation process may be used after the lithography step on the exposed areas without photoresist to continue the manufacturing process of the integrated circuit.
If there are two patterns with different sizes or different densities on the same mask, line end shortening (LES), corner rounding, iso-to-dense bias and edge-to-dense bias issues may occur on the images translated to the photoresist from the mask.
In order to resolve the foregoing issues, one conventional method involves using two masks and two exposure steps to overcome these issues. The second mask and the second exposure step are used to improve the iso-to-dense bias, the edge-to-dense bias and the line end shortening issue. Since this method needs two masks and two exposure steps, however, it can be complex and expensive. In addition, alignment issues may arise with the use of two masks.
Another conventional method used to address the foregoing issues involves the addition of sub-resolution assist features (SRAFs) to the pattern. SRAFs are small additional features on the mask near for example isolated lines which can be considered to diffract light similarly to that of dense lines. This approach has become an effective way to reduce iso-to-dense bias. As dimensions shrink and line density increases, however, even SRAFs may be too large to fit within a given pattern to effectively reduce for example line end shortening and iso-to-dense bias.
A need thus exists in the prior art to effectively and efficiently reduce issues such as iso-to-line bias for fine line patterns. A further need exists to efficiently and effectively reduce issues such as line end shortening for these fine line structures.